1. Field of the Invention
The present invention relates to the field of computer systems; more particularly, the present invention relates to performing memory read operations in a computer system.
2. Description of Related Art
Data is stored in (as a result of write operations) and retrieved from (as a result of read operations) Dynamic Random Access Memories (DRAMs) at memory locations indicated by an address. The DRAMs are organized as an array of rows and columns of memory locations. A portion of the address specifies the row where the data is located (row address) and another portion of the address specifies the column where the data is located (column address). For DRAMs that store multiple data bits per address, the column address may correspond to several physical columns within each DRAM.
The row address and the column address are typically multiplexed onto the same address bus of each DRAM. When the row address is provided on the address bus, a row-address strobe (RAS) signal is asserted to produce an edge which indicates that the row address is valid. When the column address is provided, a column-address strobe (CAS) signal is asserted to produce an edge that indicates that the column address is valid. The CAS signal causes the data at that row address and column address to be driven on the outputs of each DRAM. If another column address is specified and CAS is asserted before RAS is deasserted, the data at this column within the same row is driven on the outputs of the device. When the row-address strobe (RAS) signal is deasserted, the columns of each DRAM are precharged for the next cycle(s). Data having the same row address is said to be within the same "page." By accessing columns within the same page without deasserting RAS, the time to precharge the columns is avoided thereby improving access time.
The outputs of the DRAMs are driven onto a data bus. It takes a certain amount of time to access the memory and drive the data on the data bus (access time) after the falling edge of the CAS signal. This data is only valid for a certain period of time. The signal that causes the data to be latched (LATCH signal) must be within the period in which the data is valid on the data bus to avoid data errors. The system designer may consider device manufacturing variations (some devices are faster than others), environmental variations (voltage and temperature, for example, affect device speed), load variations (the number of DRAMs in a system may change over time, the manufacturing variations of the circuit board affect capacitance, etc.) and other sources of uncertainty in controlling the timing of LATCH signal relative to the timing of the CAS signal. This technique tends to require large timing margins. Another technique is to employ a phase-locked-loop (PLL), delay line, or other timing compensation circuit to adjust the relative timing between the LATCH signal and the CAS signal. Although this does not require large timing margins, these circuits tend to be expensive and tend to require special tuning for each circuit board design. The timing margin available depends on the type of DRAMs used.
A fast page-mode DRAM strobes a column address and drives the corresponding data on the falling edge of the CAS signal. The corresponding data is driven until the rising edge of the CAS signal. The corresponding data is not driven during the period from the rising edge of the CAS signal to the next falling edge of the CAS signal. Since the latch must latch the data while the CAS signal is low, the CAS pulse must be relatively wide (several clock cycles) to meet timing margins. The use of a wide CAS pulse limits data throughput.
An extended data output (EDO) DRAM also strobes a column address and drives the corresponding data on the falling edge of the CAS signal until the next falling edge of the CAS signal (in which case the next data is driven) or until RAS is deasserted (in which case the bus is tristated). This allows the additional time during the period from the rising edge of the CAS signal to the next falling edge of the CAS signal to be used to latch the corresponding data. Since the latch may now latch the data while the CAS pulse is high, the CAS pulse can be narrowed to a single clock thereby improving data throughput.
A burst extended data output (BEDO) DRAM also drives the corresponding data on the falling edge of the CAS signal until the next falling edge of the CAS signal or until RAS is deasserted. However, a BEDO DRAM is distinguished from an EDO DRAM in that it returns several data elements for each address provided. In addition, a BEDO DRAM is distinguished from the EDO DRAM in that one falling edge of the CAS pulse causes the BEDO DRAM to strobe the address and internally access the corresponding data and the next falling edge of the CAS pulse causes the BEDO DRAM to drive the corresponding data. Since only one address is required for every several data elements, the timing constraints for the address signals are reduced. The reduced timing constraints permit the CAS pulse to be narrowed to half a clock which further improves throughput. The narrower CAS pulse-width requires greater control of the timing of the LATCH signal relative to the timing of the CAS signal. The narrow CAS pulse width generally precludes the use of timing margins to guard against variations in timings of the LATCH and CAS signals. However, the greater sensitivity to the variation in timings is tolerated because the BEDO DRAM achieves higher performance than the EDO DRAM or the fast page-mode DRAM.
What is needed is a method to control the timing of the LATCH signal relative to the timing of the CAS signal without expensive PLL, delay line, or other timing compensation circuits. What is needed is a method to control the timing of the LATCH signal relative to the timing of the CAS signal without requiring special tuning for each circuit board design.